The present invention relates generally to the field of semiconductor devices and the manufacture of those semiconductor devices. More particularly, the present invention relates to methods for etching SiO2 with high selectivity to Si3N4 and to etching metal oxides with high selectivity to SiO2.
As computers become faster and more powerful, the semiconductor devices running those computers are becoming smaller and more complex. Many modern semiconductor devices are made of CMOS (Complimentary Metal-Oxide-Semiconductor) transistors and capacitors, in which the CMOS transistors generally include a source, drain, and gate. The gate is sometimes called a gate stack because it may include several components, such as a gate electrode and an underlying gate dielectric. Sidewall spacers (also called spacers or spacer layers) may be adjacent to the gate structure and usually include an oxide layer and a nitride layer component.
Although CMOS devices are common semiconductor devices found in many computers, they are becoming increasingly more difficult to make. One reason why it is becoming more difficult to make CMOS devices is that these devices are becoming smaller and therefore the tolerance associated with each CMOS device is becoming tighter. One method for fabricating such CMOS devices includes forming a patterned mask (e.g., photoresist mask) on a material layer disposed beneath such a mask (on an underlying layer) and then etching the material layer using the patterned photoresist mask as an etch mask. The etch mask generally is a replica of the structure to be formed (e.g., etched) in the underlying layer (or layers). As such, the etch mask has the same topographic dimensions as the structures being formed in the underlying layer(s).
Conventional integration schemes used to manufacture CMOS devices are susceptible to defects within a wafer resulting from process variations. Since CMOS devices require very tight tolerances, process variations and non-uniformities within a wafer can significantly reduce the performance of CMOS devices and the yields of those devices. One example of where variations occur is during the etching of high K dielectric materials in CMOS devices. Another example of where variations occur is during the etching of the spacer layers which usually includes an oxide layer positioned next to a nitride layer. Current processes used to etch high K dielectric materials can create defects and low yields because of over etching as illustrated in FIG. 1A. Current processes used to etch oxide layers in spacers can cause defects and low yields because other layers such as nitride layers are inadvertently etched, as illustrated in FIG. 1B.
FIG. 1A illustrates a partially fabricated CMOS device 100A before etching its high K dielectric layer and the same partially fabricated CMOS device 100B after etching its high K dielectric layer. CMOS device 100A includes a substrate 110A, a SiO2 or SiON layer 115A, a high K dielectric layer 120A, a metal gate 125A, a polysilicon layer 130A, and a nitride oxide layer 135A. Although the etching process removes the unwanted parts of the a high K dielectric layer 120A, the etching process also removes portions of the SiO2 or SiON layer 115A and the portions of the substrate 110A leaving unwanted Si recesses. The etching process also removes a portion of the nitride oxide layer 135A. CMOS device 100B includes a substrate 110B, a SiO2 or SiON layer 115B, a high K dielectric layer 120B, a metal gate 125B, a polysilicon layer 130B, a nitride oxide layer 135B and dashed ellipses showing where unwanted etching has occurred. CMOS device 100B shows that the etching process has removed portions of the high K dielectric layer leaving behind the desired high K layer 120B. However, CMOS device 100B also includes dashed ellipses illustrating that the SiO2 or SiON layer 115B and the portions of the substrate 110B have been over etched leaving unwanted Si recesses. Similarly, CMOS device 100B includes a dashed ellipse that encircle a portion of the nitride/oxide layer 135B that has been etched and is now clearly thinner than it was prior to etching (i.e. compare 135A with 135B).
FIG. 1B illustrates a simple structure representing a spacer layer having an oxide layer positioned next to a nitride layer before etching 100C and after etching 100D. Before etching, the structure 100C includes an oxide layer 160A positioned next to a nitride layer 155A on a substrate 150A. After etching, the structure 100D includes only the nitride layer 155B and substrate 150B, which have both been etched along with the oxide layer 160A as pointed out by the dashed ellipses. The dashed ellipses clearly show that the substrate 150B has been over etched leaving recesses and that the nitride layer 155B has also been etched so that it is much thinner than the original nitride layer 155A.
The problem with over etching has been addressed by using gasses that selectively etch silicon oxides instead of nitrides. Traditional means of etching silicon oxides while achieving selectivity between silicon oxides and nitrides is done using gasses having CHF3, CH2F2, or C4F8 types of chemistries. These chemistries selectively etch oxides by passivating the nitride and preventing further etch of the nitride layers. However, etching with these chemistries results in large deposition of polymer on other parts of the wafer.
Therefore, what is needed is a method of fabricating a semiconductor device by selectively etching high K dielectric films with good vertical profiles without footing and with high selectivity to SiO2 and Si. Additionally, what is needed is a method of fabricating a semiconductor device by selectively etching thin oxide cap layers on certain regions of the semiconductor device without silicon nitride loss in other regions of the device.